Cortus, the semiconductor IP company delivering processor and peripheral IP for the new wave of smart applications, has announced the release of the APS25 processor IP core, the second in a family of products based on the new Cortus v2 instruction set (see news release on APS23).
The APS25 core is aimed at embedded systems demanding greater computational performance and system complexity, while also requiring maximum code density and extendibility.
"The Internet of Things is ushering in a huge transition for embedded processors where power, security and code size are critical," said Loyd Case, senior analyst of The Linley Group. “We see a whole new set of requirements emerging for processor IP, especially when it comes to managing power and silicon area.
“The new Cortus cores and architecture do a good job of balancing between the complexity of the processor core and the size of the instruction memory, making them well suited for a broad range of industrial and consumer applications.”
Cortus licenses a range of low power 32-bit processor cores for intelligent connected devices. With growing embedded system complexity, APS25 has been designed to support accelerating computation through using coprocessors or symmetric multiprocessing. The core is also designed to be a building block in the growing number of dual-, or multi-core systems.
The APS25 has a Harvard architecture, sixteen 32-bit registers, a 5-stage pipeline, and a parallel multiplier. It supports the AXI4 bus as well as Cortus APS peripherals.
Up to eight co-processors can be added to an APS25 core. The Cortus coprocessor interface allows licensees to add custom coprocessors, for example to accelerate computations in cryptography or signal processing, without knowing details of the internals of the core. Co-processor instructions can be inserted into C-code appearing as function calls.
The small size of APS25 makes it highly suitable for applications requiring two cores. For example a common approach in functional safety is for two cores to execute the same code in lock step and to trigger an alarm if the results do not match.
Another application is secure execution where it is desirable to physically separate the execution of secure software by running it on a supervisory CPU while application code runs on another CPU core.
The Cortus v2 instruction set allows the seamless mixing of 16-, 24- and 32-bit instructions without mode switching. This instruction set is richer than the v1 instruction set which used a mix of 16- and 32-bit instructions.
Cortus will continue to offer products based on the v1 instruction set (e.g. APS5) in parallel with the new cores based on the v2 instruction set. All C/C++ or assembler code developed for the v1 cores can be used unmodified on the v2 cores.
“Embedded systems are demanding greater computational performance at lower price points than ever before,” said Michael Chapman, CEO and president of Cortus. “The universe of wirelessly connected devices is growing rapidly, creating a new and massive market opportunity.
“Just as mobile computing transformed the desktop, we now are now in the midst of another transformation. The Internet of Things, smart sensors and ubiquitous connectivity require a new type of processing platform, one which the Cortus cores are optimized for and is already in place.”
All cores interface to Cortus’ peripherals including Ethernet 10/100 MAC, USB 2.0 Device and USB 2.0 OTG via the efficient APS bus. They also share the simple vectored interrupt structure which ensures rapid, real time interrupt response, with low software overhead.
The APS tool chain and IDE (for C and C++) is available to licensees free of charge, and can be customised and branded for final customer use. Ports of various RTOSs are available such as FreeRTOS, Micrium ?C/OSII.