Cortus has unveiled the first of a new family of products based on its v2 instruction set today (7 October 2014). The APS23 core was built to deliver a new level of efficiency, ease of integration and cost of ownership for low-power, connected intelligent devices. The core reduces embedded system power by optimising the size of the instruction memory.
“The Internet of Things and other smart devices are rewriting the rules for developing systems-on-chip and fuelling huge growth for the semiconductor industry,” said Rich Wawrzyniak, senior analyst for ASIC & SoC at Semico Research.
“IoT is creating a massive universe of connected intelligent devices that place stringent demands on processor IP and potentially represent much bigger unit numbers than the mobile market. What’s needed is a minimalist approach to power, silicon area and cost without sacrificing performance or security. This is what Cortus is doing and why Semico believes the company is well-positioned to meet the needs of this emerging market.”
Cortus licenses a range of low-power, 32-bit processor cores for intelligent connected devices. Given the continuing demand to reduce power in system-on-chip (SoC) designs, Cortus has developed a second-generation (v2) instruction set aimed at reducing the size of a system’s instruction memory.
The APS23 is the first product to use the v2 instruction set and is aimed at low power always on/always listening systems and those with less demanding clock frequencies such as Bluetooth Smart. (See also: APS25 news release from Cortus).
“Cortus cores have a proven track record in low power applications such as wireless, smart sensors and touchscreen controllers,” said Michael Chapman, CEO and president of Cortus. “However we know that today’s smart applications require a new generation of IP - IP designed with a minimalistic approach to system silicon area and power consumption while also providing good cost of ownership and key functionality.
“We have focused on reducing the size of the instruction memory which is usually the largest single component in a system and are seeing an average 16% improvement in code density over our earlier (v1) cores.”
The APS23 has a Harvard architecture, sixteen 32-bit registers, a 3-stage pipeline and a sequential multiplier. It supports the AXI4-Lite bus as well as Cortus APS peripherals. The core delivers 2.83 DMIPS/MHz and 1.44 CoreMarks/MHz in computational performance.
The minimal usable APS23 CPU starts around 9.8 kgates when optimised for area. Dynamic power is 12 microwatts/MHz with a 90 nm process (Cortus cores are synthesisable and foundry independent).
The Cortus v2 instruction set allows the seamless mixing of 16-, 24- and 32-bit instructions without mode switching. This instruction set is richer than the v1 instruction set which used a mix of 16- and 32-bit instructions.
Cortus will continue to offer products based on the v1 instruction set (e.g. APS3R) in parallel with the new cores based on the v2 instruction set. All C/C++ or assembler code developed for the v1 cores can be used unmodified on the v2 cores.
All cores interface to Cortus’ peripherals including Ethernet 10/100 MAC, USB 2.0 Device and USB 2.0 OTG via the efficient APS bus. They also share the simple vectored interrupt structure, which ensures rapid, real time interrupt response, with low software overhead.
The APS tool chain and IDE (for C and C++) is available to licensees free of charge, and can be customised and branded for final customer use. Ports of various RTOSs are available such as FreeRTOS, Micrium ?C/OSII.